The present invention relates to a non-volatile semiconductor memory device and a method of forming the same, and more particularly to a non-volatile semiconductor memory device having a logic transistor region and a flash cell region isolated by a shallow trench isolation.
FIGS. 1A through 1D are fragmentary cross sectional elevation views illustrative of a conventional method of forming a conventional non-volatile semiconductor memory device having an integration of a logic transistor region and a flash cell region isolated by a shallow trench isolation.
With reference to FIG. 1A, a PAD oxide film 3 is formed over a silicon substrate 1. A stopper nitride film 4 is deposited on the PAD oxide film 3. A resist film is applied on the stopper nitride film 4. The resist film is patterned by a lithography process to form a resist pattern. A selective anisotropic etching process is carried out by use of the resist pattern as a mask to selectively etch the stopper nitride film 4, the PAD oxide film 3 and the silicon substrate 1, thereby forming shallow trench isolation grooves. Ridged portions of the silicon substrate 1 are defined by the shallow trench isolation grooves. The ridged portions of the silicon substrate 1 underlie the laminations of the PAD oxide film 3 and the stopper nitride film 4. The used resist pattern is removed. A shallow trench isolation burying oxide film 2 is deposited so that the shallow trench isolation grooves are completely buried with the shallow trench isolation burying oxide film 2, wherein the shallow trench isolation burying oxide film 2 also extends over the stopper nitride film 4.
With reference to FIG. 1B, a chemical mechanical polishing process is carried out to planarize a surface of the shallow trench isolation burying oxide film 2, whereby the top surface of the stopper nitride film 4 is exposed and slightly polished. As a result, a planarized surface is formed, wherein the top surface of the stopper nitride film 4 is leveled to the polished top surface of the shallow trench isolation burying oxide film 2, which completely buries the shallow trench isolation grooves.
With reference to FIG. 1C, the stopper nitride film 4 and the PAD oxide film 3 are etched, wherein a time of the etching process is so controlled that the top surface of the silicon substrate 1 has the same level as the etched surface of the shallow trench isolation burying oxide film 2, whereby the shallow trench isolation burying oxide film 2 becomes the shallow trench isolation 2. Further, device formation regions of the silicon substrate 1 are defined by the shallow trench isolation 2. The shallow trench isolation 2 has adjacent surface regions to the device formation regions of the silicon substrate 1, wherein divots are formed in the adjacent surface regions. Namely, the divots are formed in the shallow trench isolation 2 and are positioned in the vicinity of the device formation regions of the silicon substrate 1.
With reference to FIG. 1D, a thin oxide film is formed over the device formation regions of the silicon substrate 1 and over the shallow trench isolations 2, wherein the thin oxide film extends over the divots. The thin oxide film has variations in thickness over the divots. A conductive film is deposited over the thin oxide film. The conductive film may, for example, comprise a polysilicon film. Laminations of the conductive film and the thin oxide film are patterned to form a first lamination of a tunnel oxide film 14 and a floating gate 9 as well as a second lamination of a gate oxide film 7 and a logic gate 8, wherein the tunnel oxide film 14 and the floating gate 9 are positioned in a flash cell region 100, whilst the gate oxide film 7 and the logic gate 8 are positioned in a logic transistor region 200. A dielectric film 10 is formed on the surface of the floating gate 9. A control gate 11 is formed on the dielectric film 10 to form a flash cell in the flash cell region 100. Further, source and drain regions are selectively formed in the device formation region of the silicon substrate 1, whereby a logic transistor is formed in the logic transistor region 200. The sequence of formation of the flash cell and the logic transistor may be optional.
The gate insulation film 7 of the logic transistor in the logic transistor region 200 has variations in thickness over the divots. The tunnel oxide film 14 of the flash cell in the flash cell region 100 also has variations 15 in thickness over the divots. The thickness of the tunnel oxide film 14 defines a width of a tunnel barrier, which further defines a threshold voltage of the flash memory. The variation in thickness of the tunnel oxide film 14 causes variation in threshold voltage of the flash memory, whereby the reliability of the flash memory is deteriorated.
In the above circumstances, it had been required to develop a novel non-volatile semiconductor memory device free from the above problem.
Accordingly, it is an object of the present invention to provide a novel non-volatile semiconductor memory device free from the above problems.
It is a further object of the present invention to provide a novel non-volatile semiconductor memory device having an integration of a logic transistor region and a flash cell region isolated by a shallow trench isolation, wherein a tunnel barrier film has a uniform thickness.
It is a still further object of the present invention to provide a novel non-volatile semiconductor memory device having an integration of a logic transistor region and a flash cell region isolated by a shallow trench isolation, wherein a tunnel barrier film does not extend over divots formed in shallow trench isolations adjacent to a device formation region in the flash cell region.
It is yet a further object of the present invention to provide a novel non-volatile semiconductor memory device having an integration of a logic transistor region and a flash cell region isolated by a shallow trench isolation, wherein the flash cell is free from variation in threshold voltage.
It is yet a further object of the present invention to provide a novel non-volatile semiconductor memory device having an integration of a logic transistor region and a flash cell region isolated by a shallow trench isolation, wherein the flash cell is free from deterioration of reliability.
It is another object of the present invention to provide a novel method of forming a non-volatile semiconductor memory device free from the above problems.
It is a further object of the present invention to provide a novel method of forming a non-volatile semiconductor memory device having an integration of a logic transistor region and a flash cell region isolated by a shallow trench isolation, wherein a tunnel barrier film has a uniform thickness.
It is a still further object of the present invention to provide a novel method of forming a non-volatile semiconductor memory device having an integration of a logic transistor region and a flash cell region isolated by a shallow trench isolation, wherein a tunnel barrier film does not extend over divots formed in shallow trench isolations adjacent to a device formation region in the flash cell region.
It is yet a further object of the present invention to provide a novel method of forming a non-volatile semiconductor memory device having an integration of a logic transistor region and a flash cell region isolated by a shallow trench isolation, wherein the flash cell is free from variation in threshold voltage.
It is yet a further object of the present invention to provide a novel method of forming a non-volatile semiconductor memory device having an integration of a logic transistor region and a flash cell region isolated by a shallow trench isolation, wherein the flash cell is free from deterioration of reliability.
The present invention provides a tunnel barrier structure comprising: a first semiconductor ridged portion having a first top surface, the first semiconductor ridged portion being defined by a groove; an insulating layer burying the groove, the insulating layer having a first upper surface which is higher in level than the first top surface of the first semiconductor ridged portion, the insulating layer having side walls extending upwardly from edges of the first top surface of the first semiconductor ridged portion; side wall insulating films provided on the side walls; and a tunnel insulating film provided on the first top surface of the first semiconductor ridged portion, the tunnel insulating film being defined by the side wall insulating films.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.